1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof. More specifically, the present invention relates to a structure of electrodes and interconnections connected to a metal insulator semiconductor field effect transistor (hereinafter referred to as MISFET) and to manufacturing method thereof.
2. Description of the Background Art
As the degree of integration of ULSIs has become higher and higher, reduction in size both in the vertical and horizontal directions of the device has been desired. In the horizontal direction, sufficient margin must be ensured taking into account an error in accuracy in alignment during lithography in various manufacturing steps. In the vertical direction, level difference should be minimized so as to enable precise patterning for lithography.
An MISFET used in a DRAM (Dynamic Random Access Memory) as an example of a conventional semiconductor device will be described with reference to the figures.
Referring to FIGS. 89 and 90, the MISFET includes a gate electrode 105 formed on a semiconductor substrate 101 with a gate insulating film 104 interposed. There are impurity diffusion regions in semiconductor substrate 101 on both sides of the gate electrode, which provide source.multidot.drain regions 103 of the MISFET. Such MISFETs are electrically separated from each other by en element isolating insulating film 102 and a channel stop layer 111. Gate electrode 105 is formed of a conductive film such as a polycrystalline silicon film or a metal silicide film, and it constitutes a part of a word line 105. There is a bit line 108 crossing word line 105. Bit line 108 is electrically isolated from word line 105 by an interlayer insulating film 107 so as to prevent short circuit therebetween. Bit line 108 is electrically connected to one of source/drain regions 103 of the MISFET through a contact hole. The contact hole for the bit line 108 is formed for each memory cell which is constituted by one or two MISFETs. In a DRAM, a capacitor (not shown) storing charges as information is connected to the other one of source.multidot.drain regions 103 of the MISFET.
FIG. 91 is a plan view showing an example of positional relation between each of source.multidot.drain regions 103, bit line 108 and word line 105. FIGS. 89 and 90 are cross sections taken along the lines A--A and B--B of FIG. 91, respectively. Referring to FIG. 91, the conventional semiconductor device has such a structure in that word line 105 is formed and bit line 108 is formed further thereon. Therefore, there is much level difference in the vertical direction because of a step at the crossing portion, for example. Meanwhile, the contact hole must be formed such that it does not contact word line 105 and that it is surely connected to one of the source.multidot.drain regions 103. Further, short circuit between the contact hole and a channel stop layer 111 through element isolating insulating film 102 shown in FIG. 90 must be prevented. Therefore, in arranging the contact hole, accuracy in alignment in the horizontal direction at the time of lithography of the contact hole must be taken into account. For example, the distance between an end of the contact hole and an end of the source.multidot.drain region and the distance from an end of the contact hole to an end of the word line must be made wider actually by about 0.3 .mu.m than the distance in design.
Another example of a conventional semiconductor device will be described with reference to the figures. FIG. 92 is a cross section taken along the line B--B of FIG. 93. In FIG. 92, part of the gate electrode 105 rests on element isolating insulating film 102. There is a word line 109 connected to this portion resting on the element insulating isolating film through a conductive layer filled in contact hole 110. Word line 109 is formed to extend in a direction crossing gate electrode 105. Word line 109 and gate electrode 105 are isolated by an interlayer insulating film 107. Referring to FIG. 93, impurity diffusion layer forming source.multidot.drain regions 103 constitutes a bit line. In this structure, in order to connect word line 109 and gate electrode 105, it is necessary to extend a portion of gate electrode 105 in the horizontal direction, which prevents improvement in the degree of integration in the horizontal direction. Further, an interlayer insulating film through which the contact hole is formed is necessary, which results in large level difference in the vertical direction.
Japanese Patent Laying-Open No. 1-106469 discloses, as a structure for relaxing level difference between electrodes and interconnections connected to the MISFET, an example in which various electrodes are embedded in an insulating film, and a part of each of the electrode is exposed at a plane approximately flush with the surface of the insulating film. This example will be described with reference to FIGS. 94 and 95. FIG. 94 is a cross section taken along the line A--A of FIG. 95. As shown in FIG. 94 or 95, the semiconductor device includes an MOS transistor having contact electrodes 141 connected to a pair of source.multidot.drain regions 137 and a gate electrode 139 formed on a region (channel region) between the source.multidot.drain regions, with a gate insulating film 135 interposed. The MOS transistor is electrically isolated from other MOS transistors by an element isolating insulating film 133. Two contact electrodes 141 and gate electrode 139 of the transistor are electrically isolated from each other by an insulating film 143. Here, insulating film 143 and electrodes 141 and 139 are formed such that the surface of the insulating film 143 is approximately flush with the top surfaces of the electrodes. Therefore, interconnections connected to respective electrodes are approximately at the same level, thus difference in level can be reduced. However, interconnection 145 connected to gate electrode 139 cannot be formed but along the gate electrode 139 because of restriction in the method of forming. Therefore, in the MOS transistor constituting a memory cell of a memory device, for example, it is necessary that interconnection 145 connected to the contact electrode crosses interconnection 145 connected to gate electrode 139, and at that time, the interconnections must cross each other with a difference in level to prevent short-circuit. Further, it may be sometimes necessary to detour the interconnection 145 in order to prevent short-circuit. Therefore, there is inevitably a difference in level between the interconnections, which may result in difficulty in processing or lithography in the succeeding steps, or enlargement of the region for forming interconnections in the horizontal direction.
As described above, in the conventional semiconductor device, in order to connect a gate electrode and a word line of an MISFET as an example of a semiconductor device, it is necessary to extend part of the gate electrode in the horizontal direction. This hinders improvement in the degree of integration in the horizontal direction of the device. Further, there is generated a difference in level when interconnections to be connected to the electrodes of the MISFET cross each other, or there is a necessity that interconnections are detoured, resulting in difficulty in processing or photolithography in the succeeding steps and region for forming the interconnection layers in the horizontal direction tends to be widened.